CPU Caches

  • L1/L2 caches present on every core.
  • L3 caches are shared across all cores.

A cache line is the unit of data transfer between the cache and main memory. Typically the cache line is 64 bytes. The processor will read or write an entire cache line when any location in the 64 byte region is read or written. The processors also attempt to prefetch cache lines by analyzing the memory access pattern of a thread.

Cache organization works better for data structures that are stored by value.

If the cache line containing the byte or word you’re loading is not already present in the cache, your CPU will request the 64 bytes that begin at the cache line boundary (the largest address below the one you need that is multiple of 64).

Cache coherence may be implemented at the processor level but, unless the processor memory model guarantees sequential consistency (which is not the case on most modern architectures), you will only get cache coherence if you ask for it. That is what volatile is for: it asks the JVM to produce the relevant machine instruction(s) that will ask the processor(s) to synchronize its cache with main memory.

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